The present invention is generally directed to network interface cards and, more specifically, to a circuit for simultaneously reprogramming microcontrollers in multiple network interface cards.
The demand for high-performance computers and communication devices requires that state-of-the-art networks and network interface devices operate at comparable high-performance levels. The necessary high-performance is provided by network interface cards (NIC) that operate at ever increasing speeds. These network interface cards (NIC) are used in a wide variety of devices, including personal computers, switches, routers, hubs, bridges, and the like. Network interface cards operating at 10 Mbps (i.e., 10BaseT) over Category-3 (CAT3) wires and network cards operating at 100 Mbps (i.e., 100BaseT) over Category-5 (CAT5) are in common use in Ethernet local area network (LAN) environments. Additionally, network interface cards that operate at 1 Gbps (i.e., 1000BaseT) are now coming into use in Gigabit Ethernet LANs.
U.S. patent application Ser. Nos. 09/713,389 and 09/713,643, incorporated by reference above, disclose reprogrammable microcontroller architectures for controlling the physical layers of network interface cards. In the microcontrollers disclosed therein, the embedded control program of the internal ROMs can be augmented, patched around, and even replaced by new control program code that is downloaded into internal RAM via a management interface. Although the systems and methods disclosed in application Ser. Nos. 09/713,389 and 09/713,643 are important and useful features for future code updates, debugging and diagnostics, the disclosed systems and apparatuses require an external host personal computer (PC) to control the replacement program downloading operation. In a non-PC environment, such as a router or switch, an alternative mechanism is required to download a replacement program into the multiple interface cards of the router, switch, hub, bridge, or the like.
There is therefore a need in the art for an improved system for upgrading or modifying the embedded control program in a plurality of network interface cards. In particular, there is a need for a reprogramming interface circuit that can simultaneously reprogram a plurality of network interface cards. More particularly, there is a need for a fault-tolerant reprogramming interface circuit that can simultaneously reprogram a plurality of network interface cards even if one or more of the interface cards is malfunctioning.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a communication device comprising a plurality of network interface cards for communicating with an external data network, an apparatus for simultaneously transferring a replacement program into a plurality of dedicated memories in the plurality of network interface cards. According to an advantageous embodiment of the present invention, the apparatus comprises: 1) a replacement program memory capable of storing the replacement program; 2) a first microcontroller coupled to the replacement program memory and having a first dedicated memory associated therewith; and 3) a second microcontroller coupled to the replacement program memory and having a second dedicated memory associated therewith. After a power reset has occurred, the first microcontroller monitors a first signal line to the replacement program memory to determine if the second microcontroller is transferring the replacement program from the replacement program memory to the second dedicated memory and wherein the first microcontroller, in response to a determination that the second microcontroller is transferring the replacement program, transfers at least a portion of the replacement program to the first dedicated memory as the replacement program is read from the replacement program memory by the second microcontroller.
According to one embodiment of the present invention, the first microcontroller monitors the first signal line for a first predetermined period of time to determine if the second microcontroller is transferring the replacement program.
According to another embodiment of the present invention, the first microcontroller, at an expiration of the first predetermined period of time and in response to a determination that the second microcontroller is not transferring the replacement program, transfers the replacement program from the replacement program memory to the first dedicated memory.
According to still another embodiment of the present invention, a length of the first predetermined period of time is determined by a fixed address applied by a resistor matrix to address pins of the first microcontroller.
According to yet another embodiment of the present invention, the replacement program memory comprises a serial electronically erasable programmable read only memory (EEPROM).
According to a further embodiment of the present invention, the apparatus as set forth in claim 5 wherein serial EEPROM is coupled to the first and second microcontrollers by a serial data line and a serial clock line.
According to a still further embodiment of the present invention, the serial data line and a serial clock line are used to transfer the replacement program from the replacement program memory to the first and second dedicated memories.
According to a yet further embodiment of the present invention, after a power reset has occurred, the second microcontroller monitors the first signal line to the replacement program memory to determine if the first microcontroller is transferring the replacement program from the replacement program memory to the first dedicated memory and the second microcontroller, in response to a determination that the first microcontroller is transferring the replacement program, transfers at least a portion of the replacement program to the second dedicated memory as the replacement program is read from the replacement program memory by the first microcontroller.
In one embodiment of the present invention, the second microcontroller monitors the first signal line for a second predetermined period of time to determine if the first microcontroller is transferring the replacement program.
In another embodiment of the present invention, the second microcontroller, at an expiration of the second predetermined period of time and in response to a determination that the first microcontroller is not transferring the replacement program, transfers the replacement program from the replacement program memory to the second dedicated memory.
The present invention discloses an inexpensive and fully autonomous mechanism for downloading program code into internal RAM by means of a 2-wire serial EEPROM (electrically erasable PROM) In addition, the present invention addresses the ability to download code into multiple microcontrollers using only a single serial EEPROM. Since the serial EEPROM is write-able as well as read-able, updated code can be uploaded to the serial EEPROM via the management interface of the microcontrollers also.
The present invention permits the simultaneous reprogramming of multiple microcontroller in an non-managed switch (i.e., where no station manager is present to perform this function) or similar data transfer device. The present invention also allows the reprogramming of a microcontroller even when one (or more) of the other microcontrollers in the system are defective and cannot be programmed.
The present invention achieves the following objectives or has the following advantages:
1) Autonomous programming of multiple microcontrollers via a 2-wire interface to a single serial EEPROM.
2) The failure of any microcontroller does not prevent any other microcontroller from being programmed.
3) Any microcontroller can be programmed at any give time, individually or together, after a hardware reset or management power down sequence.
4) No additional hardware other than a single serial EEPROM is required.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.